The present invention relates, in general, to a circuit for receiving data and, in particular, to a method and digital circuit for decoding and recovering a clock signal from an incoming stream of Coded Marked Inversion (CMI) encoded data.
In applications relating to the transmission of digital data, for example, across an optical fiber link, the format of the transmitted optical signal is always of concern. This is an important consideration because the decision circuitry in the receiver must be able to extract precise timing information from the incoming optical signal. Three main purposes of the timing information are to allow the signal to be sampled by the receiver at the time the signal-to-noise ratio is a maximum, to maintain the proper pulse spacing, and to indicate the start and end of each timing interval. In addition, since errors resulting from noise and distortion can occur in the signal detection process, it may be desirable for the optical signal to have an inherent error-detecting capability. These features can be incorporated into the data stream by encoding the signal according to, for example, the CMI format which is a well-known technique.
The CMI format is a two-level line code in which each bit of the digital data is converted into a pair of data bits. An example of a stream of digital data being converted from the Non-Return-to-Zero (NRZ) format to the CMI format is shown in FIG. 1. Specifically, a data bit of "0" is converted into a pair of data bits "0,1", and a data bit of "1" is converted alternately into a pair of data bits "0,0" and "1,1". The pair of data bits "1,0" is, by definition, an illegal combination. The converted pair of data bits, i.e., "0,1", "0,0", or "1,1", is transmitted within the same time frame (period P) in which the digital data is applied to the encoding unit.
Receivers which decode and/or extract a timing signal from an incoming stream of CMI encoded data are known. For example, U.S. Pat. No. 4,808,970 to Arnaune shows a device for decoding CMI encoded data. Arnaune discloses a circuit having a transition detector circuit, a clock recovery circuit and a decoding circuit. The transition detector detects a negative transition (i.e., from a "1" to a "0") in a coded succession of CMI encoded data. Upon each detected transition, the clock recovery circuit causes a controllable oscillator to be resynchronized. That is, the clock recovery circuit is designed so as to form a loop for controlling the time shift between each detected transition and the following rising edge of the oscillator's output. The oscillator's output is then applied to the decoder circuit for synchronizing the decoder circuit to detect transitions in the received data signal.
The clock recovery circuit disclosed in Arnaune, however, presents several disadvantages. First, the circuit is not completely synchronous, and the combination of synchronous and asynchronous circuits introduces many difficulties in implementing the circuits. Second, Arnaune's clock recovery circuit includes a controllable oscillator and analog components requiring very precise tolerances and which, therefore, are generally more expensive than corresponding elements in completely synchronous circuits.
The device of Arnaune is further disadvantageous in that there are no means of minimizing the effects of noise or jitter.
U.S. Pat. No. 4,740,998 to House relates to a circuit and method for recovery of a data clock. In particular, House discloses a source clock signal, a means for detecting state transitions in an incoming data stream (in the Non-Return-to-Zero Inverted (NRZI) form), and a counter for generating a recovered data clock. Upon the detection of any transition in the data stream, the counter is reset. A major disadvantage of this circuit, similar to the Arnaune circuit, is that no provisions are made for reducing the effects of noise or attenuating jitter. Thus, noise in the incoming data signal, for example, can easily cause either circuit to falsely detect a transition.